Invention Grant
- Patent Title: Semiconductor manufacturing method
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Application No.: US15064990Application Date: 2016-03-09
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Publication No.: US09754781B2Publication Date: 2017-09-05
- Inventor: Shinya Okuda , Kei Watanabe , Hidekazu Hayashi
- Applicant: KABUSHIKI KAISHA TOSHIBA
- Applicant Address: JP Tokyo
- Assignee: Toshiba Memory Corporation
- Current Assignee: Toshiba Memory Corporation
- Current Assignee Address: JP Tokyo
- Agency: Finnegan, Henderson, Farabow, Garrett & Dunner, L.L.P.
- Priority: JP2015-053832 20150317
- Main IPC: H01L21/311
- IPC: H01L21/311 ; H01L21/02 ; H01L21/322 ; H01L21/3205
Abstract:
A semiconductor manufacturing method in accordance with an embodiment includes feeding a first gas, which contains a component of a first film, to a reaction chamber, and forming a first film over a semiconductor substrate, which is accommodated in the reaction chamber, through plasma CVD. The semiconductor manufacturing method includes feeding a second gas to the reaction chamber after forming the first film, allowing the first gas in the reaction chamber to react on the second gas, and forming a second film, which has a composition different from that of the first film, over the surface of the first film. The semiconductor manufacturing method includes selectively removing the second film.
Public/Granted literature
- US20160276170A1 SEMICONDUCTOR MANUFACTURING METHOD Public/Granted day:2016-09-22
Information query
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