Invention Grant
- Patent Title: Semiconductor chip including a chip level based on a layout that includes both regular and irregular wires
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Application No.: US13898155Application Date: 2013-05-20
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Publication No.: US09754878B2Publication Date: 2017-09-05
- Inventor: Stephen Kornachuk , James Mali , Carole Lambert , Scott T. Becker , Brian Reed
- Applicant: Tela Innovations, Inc.
- Applicant Address: US CA Los Gatos
- Assignee: Tela Innovations, Inc.
- Current Assignee: Tela Innovations, Inc.
- Current Assignee Address: US CA Los Gatos
- Agency: Martine Penilla Group, LLP
- Main IPC: G06F17/50
- IPC: G06F17/50 ; H01L23/528

Abstract:
A plurality of regular wires are formed within a given chip level, each having a linear-shape with a length extending in a first direction and a width extending in a second direction perpendicular to the first direction. The plurality of regular wires are positioned according to a fixed pitch such that a distance as measured in the second direction between lengthwise centerlines of any two regular wires is an integer multiple of the fixed pitch. At least one irregular wire is formed within the given chip level and within a region bounded by the plurality of regular wires. Each irregular wire has a linear-shape with a length extending in the first direction and a width extending in the second direction. A distance as measured in the second direction between lengthwise centerlines of any irregular wire and any regular wire is not equal to an integer multiple of the fixed pitch.
Public/Granted literature
- US20130256898A1 Optimizing Layout of Irregular Structures in Regular Layout Context Public/Granted day:2013-10-03
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