Invention Grant
- Patent Title: Stacked semiconductor package and manufacturing method thereof
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Application No.: US14369807Application Date: 2012-12-28
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Publication No.: US09754892B2Publication Date: 2017-09-05
- Inventor: Yong-Tae Kwon , Jun-Kyu Lee
- Applicant: NEPES CO., LTD.
- Applicant Address: KR
- Assignee: NEPES CO., LTD.
- Current Assignee: NEPES CO., LTD.
- Current Assignee Address: KR
- Priority: KR10-2011-0145519 20111229
- International Application: PCT/KR2012/011769 WO 20121228
- International Announcement: WO2013/100710 WO 20130704
- Main IPC: H01L23/34
- IPC: H01L23/34 ; H01L23/538 ; H01L25/065 ; H01L23/00 ; H01L21/56 ; H01L23/31

Abstract:
Disclosed herein is a stacked semiconductor package in which semiconductor chips having various sizes are stacked. In accordance with one aspect of the present disclosure, a stacked semiconductor package includes a first semiconductor chip structure provided with a first semiconductor chip, a first mold layer surrounding the first semiconductor chip, and a first penetration electrode passing through the first mold layer and electrically connected to the first semiconductor chip, and a second semiconductor chip structure vertically stacked on the first semiconductor chip structure and provided with a second semiconductor chip and a second penetration electrode electrically connected to the first penetration electrode, wherein the first semiconductor chip structure may have the same size as the second semiconductor chip structure.
Public/Granted literature
- US20150137346A1 STACKED SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOF Public/Granted day:2015-05-21
Information query
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