Invention Grant
- Patent Title: Methods of forming semiconductor devices including determining misregistration between semiconductor levels and related apparatuses
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Application No.: US15062452Application Date: 2016-03-07
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Publication No.: US09754895B1Publication Date: 2017-09-05
- Inventor: Yang Chao , Joseph L. Hess , Keith E. Ypma , Kurt J. Bossart
- Applicant: Micron Technology, Inc.
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: TraskBritt
- Main IPC: G02F1/1333
- IPC: G02F1/1333 ; H01J9/20 ; H01L23/544 ; G06T7/00 ; G06T11/20 ; H01L21/66 ; H01L23/48 ; H01L21/67 ; H01L21/68 ; H01L25/00 ; H01L25/065

Abstract:
A method of determining a lateral misregistration between levels of a semiconductor structure comprises imaging at least one first alignment mark in a first level of the structure and at least one second alignment mark in a second level of the structure. A digital image of the first and second alignment marks is formed, each of which are defined by a set of points having an x-value and a y-value. The x-values and y-values of points defining the first alignment mark and points defining the second alignment mark are averaged to determine a center of the first alignment mark and a center of the second alignment mark. An x-coordinate and a y-coordinate of the center of the first alignment mark is subtracted from the respective x-coordinate and y-coordinate of the center of the second alignment mark to determine a lateral misregistration between the first level and the second level. Related methods of forming a semiconductor wafer, semiconductor assembles and metrology tools for use in implementing the methods are disclosed.
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