- Patent Title: Structure and method to form III-V, Ge and SiGe fins on insulator
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Application No.: US14700672Application Date: 2015-04-30
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Publication No.: US09754968B2Publication Date: 2017-09-05
- Inventor: Shogo Mochizuki , Alexander Reznicek
- Applicant: International Business Machines Corporation
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: US NY Armonk
- Agency: Harrington & Smith
- Main IPC: H01L21/18
- IPC: H01L21/18 ; H01L21/3105 ; H01L21/306 ; H01L21/304 ; H01L29/06 ; H01L21/02 ; H01L27/12 ; H01L21/8258 ; H01L21/84

Abstract:
A method provides a first substrate supporting an insulator layer having trenches formed therein; filling the trenches using an epitaxial growth process with at least semiconductor material; planarizing tops of the filled trenches; forming a first layer of dielectric material on a resulting planarized surface; inverting the first substrate wafer to place the first layer of dielectric material in contact with a second layer of dielectric material on a second substrate; bonding the first substrate to the second substrate through the first and second layers of dielectric material to form a common layer of dielectric material; and removing the first substrate and a first portion of the filled trenches to leave a second portion of the filled trenches disposed upon the common dielectric layer. The removed first portion of the filled trenches contains dislocation defects. The method then removes the insulator layer to leave a plurality of Fin structures.
Public/Granted literature
- US20160322228A1 STRUCTURE AND METHOD TO FORM III-V, Ge AND SiGe FINS ON INSULATOR Public/Granted day:2016-11-03
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