Invention Grant
- Patent Title: Deep trench isolations and methods of forming the same
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Application No.: US14840944Application Date: 2015-08-31
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Publication No.: US09754993B2Publication Date: 2017-09-05
- Inventor: Cheng-Hsien Chou , Hsiao-Hui Tseng , Chih-Yu Lai , Shih Pei Chou , Yen-Ting Chiang , Min-Ying Tsai
- Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee Address: TW Hsin-Chu
- Agency: Slater Matsil, LLP
- Main IPC: H01L21/762
- IPC: H01L21/762 ; H01L27/146 ; H01L29/06
Abstract:
A method includes performing an anisotropic etching on a semiconductor substrate to form a trench. The trench has vertical sidewalls and a rounded bottom connected to the vertical sidewalls. A damage removal step is performed to remove a surface layer of the semiconductor substrate, with the surface layer exposed to the trench. The rounded bottom of the trench is etched to form a slant straight bottom surface. The trench is filled to form a trench isolation region in the trench.
Public/Granted literature
- US20170062512A1 Deep Trench Isolations and Methods of Forming the Same Public/Granted day:2017-03-02
Information query
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