Invention Grant
- Patent Title: Reduced gate charge field-effect transistor
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Application No.: US14954499Application Date: 2015-11-30
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Publication No.: US09755066B2Publication Date: 2017-09-05
- Inventor: David Laforet , Li Juin Yip , Cedric Ouvrard
- Applicant: Infineon Technologies Austria AG
- Applicant Address: AT Villach
- Assignee: Infineon Technologies Austria AG
- Current Assignee: Infineon Technologies Austria AG
- Current Assignee Address: AT Villach
- Agency: Murphy, Bilak & Homiller, PLLC
- Main IPC: H01L21/336
- IPC: H01L21/336 ; H01L29/78 ; H01L29/66 ; H01L29/10

Abstract:
In one implementation, a reduced gate charge field-effect transistor (FET) includes a drift region situated over a drain, a body situated over the drift region, and source diffusions formed in the body. The source diffusions are adjacent a gate trench extending through the body into the drift region and having a dielectric liner and a gate electrode situated therein. The dielectric liner includes an upper segment and a lower segment, the upper segment extending to at least a depth of the source diffusions and being significantly thicker than the lower segment.
Public/Granted literature
- US20170154993A1 Reduced Gate Charge Field-Effect Transistor Public/Granted day:2017-06-01
Information query
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