Invention Grant
- Patent Title: Source and drain stressors with recessed top surfaces
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Application No.: US15443954Application Date: 2017-02-27
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Publication No.: US09755077B2Publication Date: 2017-09-05
- Inventor: Kun-Mu Li , Tsz-Mei Kwok , Hsueh-Chang Sung , Chii-Horng Li , Tze-Liang Lee
- Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee Address: TW Hsin-Chu
- Agency: Slater Matsil, LLP
- Main IPC: H01L21/02
- IPC: H01L21/02 ; H01L29/78 ; H01L27/088 ; H01L29/08 ; H01L29/165 ; H01L29/66 ; H01L21/8234
Abstract:
An integrated circuit structure includes a gate stack over a semiconductor substrate, and a silicon germanium region extending into the semiconductor substrate and adjacent to the gate stack. The silicon germanium region has a top surface, with a center portion of the top surface recessed from edge portions of the top surface to form a recess. The edge portions are on opposite sides of the center portion.
Public/Granted literature
- US20170170319A1 Source and Drain Stressors with Recessed Top Surfaces Public/Granted day:2017-06-15
Information query
IPC分类:
