A multi-bit flip-flop has first and second one-bit flip-flops. The multi-bit flip-flop employs inter-cell clock switch (CSW) sharing in which the first and second one-bit flip-flops share at least one clock switch. The multi-bit flip-flop may also employ intra-cell CSW sharing in which at least one of the first and second one-bit flip-flops shares at least one clock switch. The inter-cell CSW sharing enables implementation of multi-bit flip-flops with fewer clock switches and possibly fewer data devices, while reducing power consumption, including state retention power gating power reduction.