Invention Grant
- Patent Title: Damage reduction method and apparatus for destructive testing of power semiconductors
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Application No.: US13560233Application Date: 2012-07-27
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Publication No.: US09759763B2Publication Date: 2017-09-12
- Inventor: Rodney E. Schwartz , Steve Clauter , David Lohr , Gary Rogers , James Baggiore
- Applicant: Rodney E. Schwartz , Steve Clauter , David Lohr , Gary Rogers , James Baggiore
- Applicant Address: US AZ Temp
- Assignee: Integrated Technology Corporation
- Current Assignee: Integrated Technology Corporation
- Current Assignee Address: US AZ Temp
- Agency: Renner, Otto, Boisselle & Sklar LLP
- Main IPC: G01R1/067
- IPC: G01R1/067 ; G01R1/36 ; G01R31/12 ; G01R31/27 ; G01R31/28 ; G01R31/26 ; G01R31/02
Abstract:
A device and method for limiting damage to a semiconductor device under test when the semiconductor device fails during a high current, or high power test is provided. The occurrence of a failure of the device under test is detected, and power applied to the semiconductor device is diverted through a parallel path element upon detection of failure of the semiconductor device.
Public/Granted literature
- US20130027067A1 DAMAGE REDUCTION METHOD AND APPARATUS FOR DESTRUCTIVE TESTING OF POWER SEMICONDUCTORS Public/Granted day:2013-01-31
Information query
