Invention Grant
- Patent Title: Optimized use of hardware micro partition prefetch based on software thread usage
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Application No.: US14949924Application Date: 2015-11-24
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Publication No.: US09760491B2Publication Date: 2017-09-12
- Inventor: Hemalatha B T , Peter J. Heyrman , Bret R. Olszewski
- Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: US NY Armonk
- Agency: Law Office of Jim Boice
- Main IPC: G06F12/00
- IPC: G06F12/00 ; G06F12/084 ; G06F12/0808 ; G06F9/455 ; G06F12/0873 ; G06F9/50

Abstract:
A computer-implemented method selectively adjusts a resources addresses cache of addresses of resources used by virtual processors. A first dispatch from a hypervisor dispatches a first virtual processor, and then tracks processes executed by the first virtual processor. The hypervisor caches cache addresses of resources used by the processes after the first dispatch in a resources addresses cache. The hypervisor undispatches the first virtual processor, and then redispatches the first virtual processor as a second virtual processor by issuing a second dispatch. Processes executed by the second virtual processor are compared to processes executed during by the first virtual processor, thus leading to an identification of a level of process utilization consistency. The hypervisor then adjusts the resources addresses cache by selectively clearing resource addresses based on the level of process utilization consistency.
Public/Granted literature
- US20170132127A1 Optimized Use of Hardware Micro Partition Prefetch Based on Software Thread Usage Public/Granted day:2017-05-11
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