Invention Grant
- Patent Title: Semiconductor device design methods and conductive bump pattern enhancement methods
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Application No.: US15174795Application Date: 2016-06-06
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Publication No.: US09760670B2Publication Date: 2017-09-12
- Inventor: Tzu-Yu Wang , Wei-Cheng Wu , Kuo-Ching Hsu , Shang-Yun Hou , Shin-Puu Jeng
- Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee Address: TW Hsin-Chu
- Agency: Slater Matsil, LLP
- Main IPC: G06F17/50
- IPC: G06F17/50 ; H01L23/00

Abstract:
Semiconductor device design methods and conductive bump pattern enhancement methods are disclosed. In some embodiments, a method of designing a semiconductor device includes designing a conductive bump pattern design, and implementing a conductive bump pattern enhancement algorithm on the conductive bump pattern design to create an enhanced conductive bump pattern design. A routing pattern is designed based on the enhanced conductive bump pattern design. A design rule checking (DRC) procedure is performed on the routing pattern.
Public/Granted literature
- US20160283639A1 Semiconductor Device Design Methods and Conductive Bump Pattern Enhancement Methods Public/Granted day:2016-09-29
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