Invention Grant
- Patent Title: Memory system and memory control method
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Application No.: US15065092Application Date: 2016-03-09
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Publication No.: US09761326B2Publication Date: 2017-09-12
- Inventor: Yu Nakanishi , Daisuke Iwai , Kiwamu Watanabe , Kenji Funaoka , Tetsuya Sunata , Keigo Hara , Marie Takada
- Applicant: Toshiba Memory Corporation
- Applicant Address: JP Minato-ku
- Assignee: TOSHIBA MEMORY CORPORATION
- Current Assignee: TOSHIBA MEMORY CORPORATION
- Current Assignee Address: JP Minato-ku
- Agency: Oblon, McClelland, Maier & Neustadt, L.L.P.
- Main IPC: G11C29/00
- IPC: G11C29/00 ; G11C29/02 ; G06F11/10 ; G11C7/22 ; G11C29/42 ; G11C29/52 ; G11C29/04

Abstract:
According to one embodiment, a memory system includes: a non-volatile memory; a memory interface that reads a received word from the non-volatile memory; a decoder that decodes the received word; a control unit that predicts the number of error bits in the received word read from the non-volatile memory, predicts decoding time on the basis of the number of error bits predicted, and determines an operating clock frequency of the decoder on the basis of the predicted decoding time and requested decoding time being the decoding time requested; and a frequency control unit that supplies the operating clock frequency determined by the control unit to the decoder and supplies voltage corresponding to the operating clock frequency being determined to the decoder.
Public/Granted literature
- US20170031755A1 MEMORY SYSTEM AND MEMORY CONTROL METHOD Public/Granted day:2017-02-02
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