Invention Grant
- Patent Title: Edge structure for backgrinding asymmetrical bonded wafer
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Application No.: US14660949Application Date: 2015-03-18
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Publication No.: US09761561B2Publication Date: 2017-09-12
- Inventor: Ranjan Rajoo , Kai Chong Chan
- Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.
- Applicant Address: SG Singapore
- Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
- Current Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
- Current Assignee Address: SG Singapore
- Agency: Horizon IP Pte Ltd.
- Main IPC: H01L21/304
- IPC: H01L21/304 ; H01L25/065 ; H01L25/00 ; H01L21/768

Abstract:
Semiconductor devices and methods of forming a semiconductor device are disclosed. The device includes a wafer with top and bottom surfaces. The wafer includes edge and non-edge regions. The wafer includes a plurality of devices and partially processed TSV contacts disposed in the non-edge region and a groove disposed at the edge region. The groove enables edges of the wafer to be automatically trimmed off as the wafer is subject to a back-grinding planarization process to expose the TSV contacts in the non-edge region of the wafer.
Public/Granted literature
- US20160276310A1 EDGE STRUCTURE FOR BACKGRINDING ASYMMETRICAL BONDED WAFER Public/Granted day:2016-09-22
Information query
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