Semiconductor devices having vertical field effect transistor (FET) devices with reduced contact resistance are provided, as well as methods for fabricating vertical FET devices with reduced contact resistance. For example, a semiconductor device includes a vertical FET device formed on a substrate, and a vertical source/drain contact. The vertical FET device comprises a first source/drain region disposed on a buried insulating layer of the substrate. The first source/drain region comprises an upper surface, sidewall surfaces, and a bottom surface that contacts the buried insulating layer. The vertical source/drain contact is disposed adjacent to the vertical FET device and contacts at least one sidewall surface of the first source/drain region. The vertical source/drain contact comprises an extended portion which is disposed between the first source/drain region and the buried insulating layer and in contact with at least a portion of the bottom surface of the first source/drain region.