In one embodiment, a switch includes a processor and logic integrated with and/or executable by the processor to receive details about which link aggregation (LAG) information about a first peer switch will be exchanged with the switch, send to the first peer switch, prior to receiving the LAG information about the first peer switch, details about which LAG information about the switch will be exchanged with the first peer switch, receive the LAG information about the first peer switch, store the LAG information about the first peer switch, and use the LAG information about the first peer switch and the LAG information about the switch to determine load balancing across one or more connections between the switch and the first peer switch.