- Patent Title: Package substrate and method for manufacturing package substrate
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Application No.: US14706269Application Date: 2015-05-07
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Publication No.: US09763319B2Publication Date: 2017-09-12
- Inventor: Yasushi Inagaki , Yasuhiro Takahashi , Satoshi Kurokawa
- Applicant: IBIDEN CO., LTD.
- Applicant Address: JP Ogaki-shi
- Assignee: IBIDEN CO., LTD.
- Current Assignee: IBIDEN CO., LTD.
- Current Assignee Address: JP Ogaki-shi
- Agency: Oblon, McClelland, Maier & Neustadt, L.L.P.
- Priority: JP2014-095819 20140507
- Main IPC: H05K7/00
- IPC: H05K7/00 ; H05K1/02 ; H05K1/03 ; H05K1/11 ; H05K1/18 ; H05K3/46 ; H01L23/538 ; H01L25/18 ; H01L23/498

Abstract:
A package substrate includes an inner interlayer, a first conductor layer, a second conductor layer, an outermost interlayer, an outermost conductor layer including first and second pads to mount electronic components, vias including first and second vias such that the first vias are connecting the first conductor layer and first pads and the second vias are connecting the first conductor layer and second pads, and skip vias penetrating through the outermost and inner interlayers such that the skip vias are connecting the outermost and second conductor layers. Sum of insulation distances (t1, t2) is in range of 40 μm or less to 10 μm or more, where the insulation distance (t1) is insulation distance between the outermost and first conductor layers and the insulation distance (t2) is insulation distance between the first and second conductor layers, and difference between the insulation distances (t1, t2) is less than 5 μm.
Public/Granted literature
- US20150327363A1 PACKAGE SUBSTRATE AND METHOD FOR MANUFACTURING PACKAGE SUBSTRATE Public/Granted day:2015-11-12
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