Invention Grant
- Patent Title: Pad structure layout for semiconductor device
-
Application No.: US13929172Application Date: 2013-06-27
-
Publication No.: US09768221B2Publication Date: 2017-09-19
- Inventor: Shang-Yen Wu , I-Chih Chen , Yi-Sheng Liu , Volume Chien , Fu-Tsun Tsai , Chi-Cherng Jeng , Ying-Hao Chen
- Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee Address: TW Hsin-Chu
- Agency: Haynes and Boone, LLP
- Main IPC: H01L23/52
- IPC: H01L23/52 ; H01L27/146 ; H01L23/00

Abstract:
A semiconductor device including a light sensing region disposed on a substrate is provided that includes a bond structure having one or more patterned layers underlying the pad element. The pad element may be coupled to the light sensing region and may be formed in a first metal layer disposed on the substrate. A second metal layer of the device has a first bond region, a region of the second metal layer that underlies the pad element. This first bond region of the second metal layer includes a pattern of a plurality of conductive lines interposed by dielectric. A via connects the pad element and the second metal layer.
Public/Granted literature
- US20150001658A1 PAD STRUCTURE LAYOUT FOR SEMICONDUCTOR DEVICE Public/Granted day:2015-01-01
Information query
IPC分类: