Implementations of the present disclosure involve a system and/or method for measuring on-die voltage levels of an integrated circuit through a digital sampling circuit. In particular, the system and/or method utilize a delay line based analog-to-digital sampling circuit that produces a voltage reading over time, such as at every high frequency clock cycle. In one embodiment, the digital sampling circuit or digital voltage monitor circuit includes a coarse delay component or circuit that further delays the propagation of a clock signal through the delay line. The coarse delay circuit may be programmed to delay the propagation of the signal through the delay line in such a manner as to allow for multiple edges of a clock or test signal to travel simultaneously down the delay line and increase the sensitivity of the circuit. Additional sensitivity of the digital voltage monitor circuit may also be obtained through selection of the types of components that comprise the circuit and a clock jitter monitor circuit configured with a constant supply voltage.