A circuit division method for test pattern generation in which a computer performs processes of: acquiring, for each of a plurality of blocks included in a target circuit for test pattern generation, a first feature amount regarding a size of each block and a second feature amount regarding a function of the block; classifying the plurality of blocks into a plurality of groups so that blocks for which the acquired first feature amount is within a first predetermined range and the acquired second feature amount is within a second predetermined range belong to an identical group; and assigning, for each of the classified groups, each of the blocks included in the group to one of a plurality of divided circuits of a division number based on a ratio of the number of blocks included in the group to the division number by which the plurality of blocks are divided.