Invention Grant
- Patent Title: Semiconductor manufacturing method and tool
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Application No.: US14804186Application Date: 2015-07-20
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Publication No.: US09772561B2Publication Date: 2017-09-26
- Inventor: Yung-Yao Lee , Heng-Hsin Liu , Yi-Ping Hsieh , Ying Ying Wang
- Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee Address: TW Hsin-Chu
- Agency: Slater Matsil, LLP
- Main IPC: G03F9/00
- IPC: G03F9/00 ; G03F7/20 ; H01L21/66 ; G06F17/50 ; G01N21/95

Abstract:
An overlay measurement and correction method and device is provided. In an embodiment the measurement device takes measurements of a first semiconductor wafer and uses the measurements in a plurality of correction techniques to generate an overlay correction model. The plurality of correction techniques include a first order correction, a first intra-field high order parameter correction and a first inter-field high order parameter correction. The model is used to adjust the exposure parameters for the exposure of the next semiconductor wafer. The process is repeated on each semiconductor wafer for a run-to-run analysis.
Public/Granted literature
- US20160240443A1 Semiconductor Manufacturing Method and Tool Public/Granted day:2016-08-18
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