Invention Grant
- Patent Title: Power shutdown with isolation logic in I/O power domain
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Application No.: US13629424Application Date: 2012-09-27
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Publication No.: US09772668B1Publication Date: 2017-09-26
- Inventor: Tobing Soebroto , James DeMaris , Jose L. Medero , Scott J. Tucker
- Applicant: Cadence Design Systems, Inc.
- Applicant Address: US CA San Jose
- Assignee: Cadence Design Systems, Inc.
- Current Assignee: Cadence Design Systems, Inc.
- Current Assignee Address: US CA San Jose
- Agency: Schwegman Lundberg & Woessner, P.A.
- Main IPC: G06F1/00
- IPC: G06F1/00 ; G06F1/32 ; G06F1/26

Abstract:
A circuit for that includes isolation logic is disclosed. In one aspect, circuit comprises at least one input/output (I/O) cell, the I/O cell further including circuitry functions, isolation control logic, and a capability to receive power to the I/O cell from a power domain source. In a second aspect an integrated circuit comprises a physical layer (PHY) logic and at least one input/output (I/O) cell in communication with the PHY logic. The I/O cell capable of receiving power from a plurality of power domains. The I/O cell includes an isolation control logic and an I/O logic capable of receiving power from one power domain of a plurality of power domains, wherein the I/O logic and the isolation controller are arranged in communication through a level shifter for shifting power to maintain an active operation of the at least one I/O cell; wherein since the isolation control logic is within the I/O cell, only one active power domain of the plurality of power domains is required.
Information query