Methods and apparatuses relating to a common architectural state presentation for a processor having cores of different types are described. In one embodiment, a processor includes a first core, a second core, wherein the first core comprises a unique architectural state and a common architectural state with the second core, and circuitry to migrate a thread from said first core to said second core, said circuitry to migrate the common architectural state from the first core to the second core, and migrate the unique architectural state to a storage external from the second core.