Invention Grant
- Patent Title: Logical operation circuit and memory device
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Application No.: US14974282Application Date: 2015-12-18
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Publication No.: US09773539B2Publication Date: 2017-09-26
- Inventor: Keisuke Nakatsuka
- Applicant: Keisuke Nakatsuka
- Applicant Address: JP Tokyo
- Assignee: TOSHIBA MEMORY CORPORATION
- Current Assignee: TOSHIBA MEMORY CORPORATION
- Current Assignee Address: JP Tokyo
- Agency: Holtz, Holtz & Volek PC
- Main IPC: G11C11/16
- IPC: G11C11/16 ; G11C5/06 ; H01L27/22 ; H01L43/08 ; H03K19/18

Abstract:
According to one embodiment, a logical operation circuit includes a magnetic tunnel junction (MTJ) element and driver. The MTJ element includes a first magnetic layer, a second magnetic layer, and an intermediate layer between the first and second magnetic layers. An orientation of magnetization of the second magnetic layer flips by a first current which flows through the MTJ element in a first state from the second magnetic layer to the first magnetic layer. The driver is coupled to the first magnetic layer without a magnetic layer interposed and coupled to the second magnetic layer, and passes a second current through the MTJ element in the first state from the second magnetic layer to the first magnetic layer. A magnitude of the second current is larger than 1.5 times a magnitude of the first current.
Public/Granted literature
- US20170076774A1 LOGICAL OPERATION CIRCUIT AND MEMORY DEVICE Public/Granted day:2017-03-16
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