Memory device with switchable sense amplifier
Abstract:
A switchable sense amplifier includes a sense amplification unit and a plurality of switches. The sense amplification unit senses a voltage change of a bit line connected to a memory cell and amplifies a voltage difference between the bit line and a complementary bit line. The plurality of switches operate according to switching signals, and thus, enable the sense amplification unit to perform a pre-charging operation, an offset cancellation operation, a charge sharing operation, a sensing operation, and a re-storing operation. The sense amplifier may enhance an effective sensing margin by compensating for an offset of the sense amplifier, through an offset cancellation operation, and thus enhance performance of a memory apparatus.
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