Invention Grant
- Patent Title: Lithography using high selectivity spacers for pitch reduction
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Application No.: US14877416Application Date: 2015-10-07
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Publication No.: US09773676B2Publication Date: 2017-09-26
- Inventor: Yu-Sheng Chang , Cheng-Hsiung Tsai , Chung-Ju Lee , Hai-Ching Chen , Hsiang-Huan Lee , Ming-Feng Shieh , Ru-Gun Liu , Shau-Lin Shue , Tien-I Bao , Tsai-Sheng Gau , Yung-Hsu Wu
- Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee Address: TW Hsin-Chu
- Agency: Slater Matsil, LLP
- Main IPC: H01L21/311
- IPC: H01L21/311 ; H01L21/033 ; H01L21/02 ; H01L21/306 ; H01L21/3213

Abstract:
A method embodiment for patterning a semiconductor device includes patterning a dummy layer over a hard mask to form one or more dummy lines. A sidewall aligned spacer is conformably formed over the one or more dummy lines and the hard mask. A first reverse material layer is formed over the sidewall aligned spacer. A first photoresist is formed and patterned over the first reverse material layer. The first reverse material layer using the first photoresist as a mask, wherein the sidewall aligned spacer is not etched. The one or more dummy lines are removed, and the hard mask is patterned using the sidewall aligned spacer and the first reverse material layer as a mask. A material used for forming the sidewall aligned spacer has a higher selectivity than a material used for forming the first reverse material layer.
Public/Granted literature
- US20160035571A1 Lithography Using High Selectivity Spacers for Pitch Reduction Public/Granted day:2016-02-04
Information query
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