Invention Grant
- Patent Title: Polishing stop layer(s) for processing arrays of semiconductor elements
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Application No.: US15097576Application Date: 2016-04-13
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Publication No.: US09773974B2Publication Date: 2017-09-26
- Inventor: Mustafa Michael Pinarbasi , Jacob Anthony Hernandez , Arindom Datta , Marcin Jan Gajek , Parshuram Balkrishna Zantye
- Applicant: SPIN TRANSFER TECHNOLOGIES, INC.
- Applicant Address: US CA Fremont
- Assignee: SPIN TRANSFER TECHNOLOGIES, INC.
- Current Assignee: SPIN TRANSFER TECHNOLOGIES, INC.
- Current Assignee Address: US CA Fremont
- Agency: Arnold & Porter Kaye Scholer LLP
- Main IPC: H01L21/00
- IPC: H01L21/00 ; H01L43/12 ; H01L27/22 ; H01L43/02

Abstract:
Described embodiments can be used in semiconductor manufacturing and employ materials with high and low polish rates to help determine a precise polish end point that is consistent throughout a wafer and that can cease polishing prior to damaging semiconductor elements. The height of the low polish rate material between the semiconductor elements is used as the polishing endpoint. Because the low polish rate material slows down the polishing process, it is easy to determine an end point and avoid damage to the semiconductor elements. An additional or alternative etch end point can be a thin layer of material that provides a very clear spectroscopy signal when it has been exposed, allowing the etch process to cease.
Public/Granted literature
- US20170033283A1 POLISHING STOP LAYER(S) FOR PROCESSING ARRAYS OF SEMICONDUCTOR ELEMENTS Public/Granted day:2017-02-02
Information query
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