- Patent Title: Biasing scheme for high voltage circuits using low voltage devices
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Application No.: US14561477Application Date: 2014-12-05
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Publication No.: US09774324B2Publication Date: 2017-09-26
- Inventor: Mayank Goel , Prasad Bhilawadi , Karthik Ns
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Schwegman Lundberg & Woessner, P.A.
- Main IPC: H03K17/687
- IPC: H03K17/687 ; H03K17/16

Abstract:
Some embodiments include apparatus and methods having a first node to receive a supply voltage, a second node to receive a first bias voltage, a third node to receive ground potential, a first circuit branch coupled between the first and second nodes, and a second circuit branch coupled between the first and third nodes. The first bias voltage is provided to a gate of a first transistor among a plurality of transistors coupled in series. The first and second circuit branches are arranged to provide a second bias voltage to gate of a second transistor among the plurality of transistors. The value of the second bias voltage is based on a value of the first bias voltage.
Public/Granted literature
- US20160164515A1 BIASING SCHEME FOR HIGH VOLTAGE CIRCUITS USING LOW VOLTAGE DEVICES Public/Granted day:2016-06-09
Information query
IPC分类: