A sample and hold circuit takes a sample of the current flowing through an inductor of a buck switched-mode power supply (SMPS) at substantially the middle of the low side portion (50 percent point during low side switch ON) of the pulse width modulation (PWM) period. This sample of the current through the SMPS inductor during the low side ON 50% point may be considered as the “average” or “DC output” current of the SMPS, and taken every time at precisely the same low side ON 50%. A constant current source and sink are used to charge and discharge a timing capacitor whose voltage charge is monitored by a high speed voltage comparator to provide precise sample timing.