A selector circuit selects either a class upper-limit voltage or a class lower-limit voltage as a reference voltage of a comparator. A control logic controls the selector circuit, and generates a count-up signal or a count-down signal in accordance with the output of the comparator. An up/down counter counts up upon reception of the count-up signal from the control logic, and counts down upon reception of the count-down signal. A digital-analog converter outputs the class upper-limit voltage and the class lower-limit voltage in accordance with a digital value that is outputted by the up/down counter. A timer circuit is configured to be reset by the count-up signal from the control logic to the up/down counter.