Invention Grant
- Patent Title: Slow start for LDO regulators
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Application No.: US13954757Application Date: 2013-07-30
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Publication No.: US09778667B2Publication Date: 2017-10-03
- Inventor: Vincenzo F Peluso
- Applicant: QUALCOMM Incorporated
- Applicant Address: US CA San Diego
- Assignee: QUALCOMM Incorporated
- Current Assignee: QUALCOMM Incorporated
- Current Assignee Address: US CA San Diego
- Agency: Arent Fox, LLP and Qualcomm
- Main IPC: G05F1/56
- IPC: G05F1/56 ; G05F1/575 ; G05F1/46

Abstract:
Techniques for generating a control voltage for a pass transistor of a linear regulator to avoid in-rush current during a start-up phase. In an aspect, a digital comparator is provided to generate a digital output voltage comparing a function of the regulated output voltage with a reference voltage, e.g., a ramp voltage. The digital output voltage is provided to control a plurality of switches selectively coupling the gate of the pass transistor to one of a plurality of discrete voltage levels, e.g., a bias voltage or a ground voltage to turn the pass transistor on or off. In another aspect, the digital techniques may be selectively enabled during a start-up phase of the regulator, and disabled during a normal operation phase of the regulator.
Public/Granted literature
- US20150035505A1 SLOW START FOR LDO REGULATORS Public/Granted day:2015-02-05
Information query
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