Invention Grant
- Patent Title: Harmonic balance analysis memory usage estimation
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Application No.: US14476456Application Date: 2014-09-03
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Publication No.: US09779188B1Publication Date: 2017-10-03
- Inventor: Yue Li , Vuk Borich
- Applicant: Cadence Design Systems, Inc.
- Applicant Address: US CA San Jose
- Assignee: CADENCE DESIGN SYSTEMS, INC.
- Current Assignee: CADENCE DESIGN SYSTEMS, INC.
- Current Assignee Address: US CA San Jose
- Agency: Andrews Kurth Kenyon LLP
- Main IPC: G06F17/50
- IPC: G06F17/50 ; G06F17/30

Abstract:
Aspects of the present invention provide a system and method to estimate the amount of memory a harmonic balance analysis will require by measuring the memory allocated for a circuit database for a circuit undergoing harmonic balance analysis, determining the problem size of the harmonic balance analysis based on the information in the database, calculating the amount of memory for matrices, solution and auxiliary vectors needed for the harmonic balance analysis, and estimating the additional memory needed to complete a Newton iteration of the harmonic balance analysis using previously compiled statistical distributions. The total needed memory will be the sum of the measured, calculated, and estimated needed memory. A lower and an upper bound estimation of the total memory usage is provided. This information can be used by the circuit or system designer and/or an analysis or simulation tool for planning the computing resources necessary to execute the harmonic balance analysis.
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