Invention Grant
- Patent Title: Semiconductor substrate with stress relief regions
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Application No.: US15090904Application Date: 2016-04-05
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Publication No.: US09779935B1Publication Date: 2017-10-03
- Inventor: Simone Lavanga , Uttiya Chowdhury
- Applicant: Infineon Technologies Austria AG
- Applicant Address: AT Villach
- Assignee: Infineon Technologies Austria AG
- Current Assignee: Infineon Technologies Austria AG
- Current Assignee Address: AT Villach
- Agency: Murphy, Bilak & Homiller, PLLC
- Main IPC: H01L21/02
- IPC: H01L21/02 ; H01L29/15 ; H01L29/20 ; H01L29/205 ; H01L29/66 ; H01L29/778 ; H01L29/04

Abstract:
A crystalline base substrate including a first semiconductor material and having a main surface is provided. The base substrate is processed so as to damage a lattice structure of the base substrate in a first region that extends to the main surface without damaging a lattice structure of the base substrate in second regions that are adjacent to the first region. A first semiconductor layer of a second semiconductor material is formed on a portion of the main surface that includes the first and second regions. A third region of the first semiconductor layer covers the first region of the base substrate, and a fourth region of the first semiconductor layer covers the second region of the base substrate. The third region has a crystalline structure that is disorganized relative to a crystalline structure of the fourth region. The first and second semiconductor materials have different coefficients of thermal expansion.
Public/Granted literature
- US20170287709A1 Semiconductor Substrate with Stress Relief Regions Public/Granted day:2017-10-05
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