Invention Grant
- Patent Title: Semiconductor device and fabrication method for the same
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Application No.: US15013946Application Date: 2016-02-02
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Publication No.: US09780039B2Publication Date: 2017-10-03
- Inventor: Tsutomu Oosuka , Hisashi Ogawa , Yoshihiro Sato
- Applicant: Pannova Semic, LLC
- Applicant Address: US CA Santa Clara
- Assignee: PANNOVA SEMIC, LLC
- Current Assignee: PANNOVA SEMIC, LLC
- Current Assignee Address: US CA Santa Clara
- Agency: Convergent Law Group LLP
- Priority: JP2007-282678 20071031
- Main IPC: H01L21/768
- IPC: H01L21/768 ; H01L23/535 ; H01L29/78 ; H01L21/285 ; H01L21/8234 ; H01L27/11 ; H01L29/161

Abstract:
The semiconductor device includes: a transistor having a gate electrode formed on a semiconductor substrate and first and second source/drain regions formed in portions of the semiconductor substrate on both sides of the gate electrode; a gate interconnect formed at a position opposite to the gate electrode with respect to the first source/drain region; and a first silicon-germanium layer formed on the first source/drain region to protrude above the top surface of the semiconductor substrate. The gate interconnect and the first source/drain region are connected via a local interconnect structure that includes the first silicon-germanium layer.
Public/Granted literature
- US20160163649A1 SEMICONDUCTOR DEVICE AND FABRICATION METHOD FOR THE SAME Public/Granted day:2016-06-09
Information query
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