Invention Grant
- Patent Title: Stacked semiconductor package including reconfigurable package units
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Application No.: US14884916Application Date: 2015-10-16
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Publication No.: US09780071B2Publication Date: 2017-10-03
- Inventor: Sang Eun Lee , Eun Ko , Yong Jae Park
- Applicant: SK hynix Inc.
- Applicant Address: KR Icheon-si, Gyeonggi-do
- Assignee: SK hynix Inc.
- Current Assignee: SK hynix Inc.
- Current Assignee Address: KR Icheon-si, Gyeonggi-do
- Agency: William Park & Associates Ltd.
- Priority: KR10-2015-0099942 20150714
- Main IPC: H01L25/065
- IPC: H01L25/065 ; H01L23/498 ; H01L23/31

Abstract:
A semiconductor package may include a first semiconductor chip having a plurality of first bonding pads arranged at a first pitch on a first active surface. The semiconductor package may include one or more reconfigurable package units each including a second semiconductor chip having a plurality of second bonding pads arranged at a second pitch on a second active surface; a semiconductor chip connector arranged spaced apart from the second semiconductor chip and having a plurality of through vias arranged at the first pitch; a molding layer surrounding side surfaces of the second semiconductor chip and the semiconductor chip connector; and redistribution lines formed over the second semiconductor chip, the semiconductor chip connector, and the molding layer. The semiconductor package may include coupling members interposed between the first bonding pads of the first semiconductor chip and the through vias of the reconfigurable package unit and between the respective through vias of the stacked reconfigurable package units.
Public/Granted literature
- US20170018527A1 SEMICONDUCTOR PACKAGE HAVING A PLURALITY OF SEMICONDUCTOR CHIPS STACKED THEREIN Public/Granted day:2017-01-19
Information query
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