- Patent Title: Insulated gate type semiconductor device having floating regions at bottom of trenches in cell region and circumferential region and manufacturing method thereof
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Application No.: US15104332Application Date: 2014-08-04
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Publication No.: US09780205B2Publication Date: 2017-10-03
- Inventor: Jun Saito , Hirokazu Fujiwara , Tomoharu Ikeda , Yukihiko Watanabe , Toshimasa Yamamoto
- Applicant: Jun Saito , Hirokazu Fujiwara , Tomoharu Ikeda , Yukihiko Watanabe , Toshimasa Yamamoto
- Applicant Address: JP Toyota JP Kariya
- Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHA,DENSO CORPORATION
- Current Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHA,DENSO CORPORATION
- Current Assignee Address: JP Toyota JP Kariya
- Agency: Oliff PLC
- Priority: JP2013-269264 20131226
- International Application: PCT/JP2014/070520 WO 20140804
- International Announcement: WO2015/098167 WO 20150702
- Main IPC: H01L29/78
- IPC: H01L29/78 ; H01L21/761 ; H01L29/06 ; H01L29/16 ; H01L29/66 ; H01L21/04

Abstract:
A technique disclosed herein improves a voltage resistance of an insulated gate type semiconductor device. A provided method is a method for manufacturing an insulated gate type switching device configured to switch between a front surface electrode and a rear surface electrode. The method includes implanting a first kind of second conductivity type impurities to bottom surfaces of gate trenches and diffusing the implanted first kind of second conductivity type impurities, and implanting a second kind of second conductivity type impurities to the bottom surfaces of the circumferential trenches and diffusing the implanted second kind of second conductivity type impurities.
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