A system may include a memory that includes a plurality of pages, a processor, and a translation lookaside buffer (TLB) that includes a plurality of entries. The processor may be configured to access data from a subset of the plurality of pages dependent upon a first virtual address. The TLB may be configured to compare the first virtual address to respective address information included in each entry of the plurality of entries. The TLB may be further configured to add a new entry to the plurality of entries in response to a determination that the first virtual address fails to match the respective address information included in each entry of the plurality of entries. The new entry may include address information corresponding to at least two pages of the subset of the plurality pages.