High density mapping for multiple converter samples in multiple lane interface
Abstract:
An apparatus having a plurality of buffers, a first circuit and a second circuit is disclosed. The buffers are configured to store a plurality of frames to be transmitted in a plurality of respective lanes of a communication channel. The first circuit is configured to (i) generate a plurality of first groups from a first number of a plurality of samples, at least one of the first groups contains an initial portion of a given one of the samples, and (ii) generate a first of the frames by appending the first groups. The second circuit is configured to (i) receive a final portion of the given sample from the first circuit, (ii) generate a plurality of second groups from the final portion of the given sample and a second number of the samples and (iii) generate a second of the frames by appending the second groups.
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