Aspects of the disclosed technology relate to techniques of connectivity-aware reduction of layout data. With various implementations of the disclosed technology, circuit elements of interest are selected in a circuit design which includes netlist information and layout data. Based at least on pins for the circuit elements of interest, the circuit elements of interest, or both, nets of interest are determined. Cells of interest, comprising cells that are identified based at least on pins for the circuit elements of interest, the circuit elements of interest, or both, are then determined. Based on the nets of interest and the cells of interest, layout geometric elements are selected and may be analyzed for design verification. For electrostatic discharge (ESD) protection verification, the cells of interest may further comprise cells that include portions of power supply grids on top metal layers.