Gate driver on array circuit and display using the same
Abstract:
A GOA circuit includes GOA circuit units. The GOA circuit units at every two stages share a pull-down circuit. The pull-down circuit includes a first transistor, a second transistor and a third transistor. The present invention uses fewer transistors for the GOA circuit and lower the frequency of the first and second clock signals. The decrease in the frequency of the first and second clock signals helps a decrease in the frequency of charge and discharge to the parasitic capacitance and further a reduction in overall power consumption of the GOA circuit.
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