A display system includes a processor coupled to receive image data from an image source and a frame timing circuit. The processor is coupled to output the image data and first sync signals, where each one of the first sync signals is output after M number of pixel values of the image data are output from the processor. The frame timing circuit is coupled to the processor to receive the image data and the first sync signals. The frame timing circuit is coupled to output X number of pixel values of the image data and second sync signals to a display, where the X number of pixel values is an integer multiple of the M number of pixel values of the image data. Each one of the second sync signals is output after X number of pixel values of the image data are output from the frame timing circuit.