Invention Grant
- Patent Title: Shielded three-layer patterned ground structure
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Application No.: US15220175Application Date: 2016-07-26
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Publication No.: US09786331B1Publication Date: 2017-10-10
- Inventor: Albert John Wallash
- Applicant: Western Digital Technologies, Inc.
- Applicant Address: US CA San Jose
- Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
- Current Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
- Current Assignee Address: US CA San Jose
- Agency: Patterson & Sheridan, LLP
- Main IPC: G11B33/14
- IPC: G11B33/14 ; H05K1/02 ; G06F1/18

Abstract:
The present disclosure generally relates to a shielded three-layer patterned ground structure in a PCB. The PCB may be disposed in a hard disk drive. To reduce costs, PCBs are being made with only four total layers separated by dielectric material. Conductive traces in PCBs can have the problem of common mode current flowing through the traces and thus increasing the magnitude of EMI noise. By providing a shielded three-layer patterned ground structure, not only is the cost reduced, but so is the common mode current and the magnitude of EMI noise, all without any negative impact to the differential signal.
Information query
IPC分类: