Invention Grant
- Patent Title: Memory control circuit and cache memory
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Application No.: US15059842Application Date: 2016-03-03
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Publication No.: US09786342B2Publication Date: 2017-10-10
- Inventor: Hiroki Noguchi , Shinobu Fujita
- Applicant: KABUSHIKI KAISHA TOSHIBA
- Applicant Address: JP Tokyo
- Assignee: Kabushiki Kaisha Toshiba
- Current Assignee: Kabushiki Kaisha Toshiba
- Current Assignee Address: JP Tokyo
- Agency: Finnegan, Henderson, Farabow, Garrett & Dunner, L.L.P.
- Priority: JP2013-185695 20130906
- Main IPC: G11C11/00
- IPC: G11C11/00 ; G11C11/16 ; G06F12/0862 ; G06F12/0897

Abstract:
A memory control circuit to control a first memory comprising a plurality of MRAM cells, each MRAM cell including of a magnetoresistive element to store data, has a second memory, when there is a read request to a first address of the first memory, to read data of a second address different from the first address, from the first memory and store the read data, a controller to control access to the first memory and the second memory, a capacitor connected in series to the magnetoresistive element, and a sense amplifier to sense a logic of the data from a voltage between both electrodes of the capacitor, the voltage varying in accordance with a current flowing through the magnetoresistive element.
Public/Granted literature
- US20160189761A1 MEMORY CONTROL CIRCUIT AND CACHE MEMORY Public/Granted day:2016-06-30
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