Invention Grant
- Patent Title: Nonvolatile memory device, operating method thereof, and test system for optimizing erase loop operations
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Application No.: US14722796Application Date: 2015-05-27
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Publication No.: US09786374B2Publication Date: 2017-10-10
- Inventor: Jae Won Cha
- Applicant: SK hynix Inc.
- Applicant Address: KR Icheon-si, Gyeonggi-do
- Assignee: SK hynix Inc.
- Current Assignee: SK hynix Inc.
- Current Assignee Address: KR Icheon-si, Gyeonggi-do
- Agency: William Park & Associates Ltd.
- Priority: KR10-2015-0038209 20150319
- Main IPC: G11C16/16
- IPC: G11C16/16 ; G11C16/14 ; G11C29/50 ; G11C16/34 ; G11C29/02 ; G11C29/04

Abstract:
A nonvolatile memory device includes a plurality of memory blocks. The nonvolatile memory device includes a controller configured to perform an erase operation by repeating an erase loop, and generates and stores a test result based on a pass erase loop count of the erase operation in response to a result processing command. The erase loop includes applying an erase voltage to a target memory block among the memory blocks in response to an erase command.
Public/Granted literature
- US20160276033A1 NONVOLATILE MEMORY DEVICE, OPERATING METHOD THEREOF, AND TEST SYSTEM HAVING THE SAME Public/Granted day:2016-09-22
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