Invention Grant
- Patent Title: Chip package method for reducing chip leakage current
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Application No.: US15340518Application Date: 2016-11-01
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Publication No.: US09786521B2Publication Date: 2017-10-10
- Inventor: Xiaochun Tan
- Applicant: Silergy Semiconductor Technology (Hangzhou) LTD
- Applicant Address: CN Hangzhou
- Assignee: Silergy Semiconductor Technology (Hangzhou) LTD
- Current Assignee: Silergy Semiconductor Technology (Hangzhou) LTD
- Current Assignee Address: CN Hangzhou
- Agent Michael C. Stephens, Jr.
- Priority: CN201510849034 20151127
- Main IPC: H01L23/538
- IPC: H01L23/538 ; H01L21/56 ; H01L23/495 ; H01L23/498 ; H01L21/683

Abstract:
A chip package method can include: forming bonding pins on a first region of a first surface of a carrier; forming an insulating layer on an inactive face of a chip, where the inactive face of the chip is opposite to an active face of the chip; pasting the chip on a second region of the first surface of the carrier by the insulating layer; electrically coupling electrodes on the active face of the chip to the bonding pins by conductive wires; forming an enclosure to cover the chip and the bonding pins by a molding process; and peeling away the carrier from the enclosure to expose the bonding pins and the insulating layer on a surface of the enclosure.
Public/Granted literature
- US20170154793A1 CHIP PACKAGE METHOD AND CHIP PACKAGE STRUCTURE Public/Granted day:2017-06-01
Information query
IPC分类: