Invention Grant
- Patent Title: Integrated circuit structure and method of forming the same
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Application No.: US14929040Application Date: 2015-10-30
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Publication No.: US09786592B2Publication Date: 2017-10-10
- Inventor: Jeng-Shyan Lin , Dun-Nian Yaung , Hsing-Chih Lin , Jen-Cheng Liu , Min-Feng Kao , Hsun-Ying Huang
- Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
- Applicant Address: TW Hsinchu
- Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
- Current Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
- Current Assignee Address: TW Hsinchu
- Agency: Maschoff Brennan
- Main IPC: H01L23/522
- IPC: H01L23/522 ; H01L23/528 ; H01L21/768 ; H01L23/48 ; H01L23/525

Abstract:
An integrated circuit structure with a back side through silicon via (B/S TSV) therein and a method of forming the same is disclosed. The method includes the steps of: receiving a wafer comprising a substrate having a front side that has a conductor thereon and a back side; forming a back side through silicon via (B/S TSV) from the back side of the substrate to penetrate the substrate; and filling the back side through silicon via (B/S TSV) with a conductive material to form an electrical connection with the conductor. Thus a back side through silicon via penetrates the back side of the substrate and electrically connects to the conductor on the front side of the substrate is formed.
Public/Granted literature
- US20170125341A1 INTEGRATED CIRCUIT STRUCTURE AND METHOD OF FORMING THE SAME Public/Granted day:2017-05-04
Information query
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