Invention Grant
- Patent Title: Method for manufacturing a semiconductor package
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Application No.: US15235439Application Date: 2016-08-12
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Publication No.: US09786611B2Publication Date: 2017-10-10
- Inventor: Kiyoaki Hashimoto , Yasuyuki Takehara
- Applicant: J-DEVICES CORPORATION
- Applicant Address: JP Oita
- Assignee: J-DEVICES CORPORATION
- Current Assignee: J-DEVICES CORPORATION
- Current Assignee Address: JP Oita
- Agency: Typha IP LLC
- Priority: JP2014-125982 20140619; JP2015-063728 20150326; JP2015-106230 20150526
- Main IPC: H01L21/00
- IPC: H01L21/00 ; H01L23/00 ; H01L23/544 ; H01L23/36 ; H01L23/373 ; H01L21/48 ; H01L23/31 ; H01L21/56 ; H01L23/538 ; H01L23/498 ; H01L25/065

Abstract:
A semiconductor package includes a support substrate; a stress relaxation layer provided on a main surface of the support substrate; a semiconductor device located on the stress relaxation layer; an encapsulation material covering the semiconductor device, the encapsulation material being formed of an insulating material different from that of the stress relaxation layer; a line running through the encapsulation material and electrically connected to the semiconductor device; and an external terminal electrically connected to the line. Where the support substrate has an elastic modulus of A, the stress relaxation layer has an elastic modulus of B, and the encapsulation material has an elastic modulus of C under a same temperature condition, the relationship of A>C>B or C>A>B is obtained.
Public/Granted literature
- US20160351511A1 SEMICONDUCTOR PACKAGE Public/Granted day:2016-12-01
Information query
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