Invention Grant
- Patent Title: Semiconductor structure and manufacturing method thereof
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Application No.: US14942961Application Date: 2015-11-16
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Publication No.: US09786618B2Publication Date: 2017-10-10
- Inventor: Chang-Pin Huang , Hsien-Ming Tu , Ching-Jung Yang , Shih-Wei Liang , Hung-Yi Kuo , Yu-Chia Lai , Hao-Yi Tsai , Chung-Shi Liu , Chen-Hua Yu
- Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
- Applicant Address: TW Hsinchu
- Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
- Current Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
- Current Assignee Address: TW Hsinchu
- Agency: WPAT, P.C., Intelllectual Property Attorneys
- Agent Anthony King
- Main IPC: H01L23/48
- IPC: H01L23/48 ; H01L23/00 ; H01L23/522 ; H01L23/532

Abstract:
A semiconductor structure includes a die including a die pad disposed over the die; a conductive member disposed over and electrically connected with the die pad; a molding surrounding the die and the conductive member; and a redistribution layer (RDL) disposed over the molding, the conductive member and the die, and including a dielectric layer and an interconnect structure, wherein the interconnect structure includes a land portion and a plurality of via portions, the land portion is disposed over the dielectric layer, the plurality of via portions are protruded from the land portion to the conductive member through the dielectric layer, and each of the plurality of via portions at least partially contacts with the conductive member.
Public/Granted literature
- US20170141056A1 SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF Public/Granted day:2017-05-18
Information query
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