Invention Grant
- Patent Title: Semiconductor device and method of forming PoP semiconductor device with RDL over top package
-
Application No.: US14660840Application Date: 2015-03-17
-
Publication No.: US09786623B2Publication Date: 2017-10-10
- Inventor: Yaojian Lin
- Applicant: STATS ChipPAC, Ltd.
- Applicant Address: SG Singapore
- Assignee: STATS ChipPAC Pte. Ltd.
- Current Assignee: STATS ChipPAC Pte. Ltd.
- Current Assignee Address: SG Singapore
- Agency: Patent Law Group: Atkins and Associates, P.C.
- Agent Robert D. Atkins
- Main IPC: H01L25/065
- IPC: H01L25/065 ; H01L25/00 ; H01L25/16 ; H01L21/56 ; H01L21/66 ; H01L21/768 ; H01L23/31 ; H01L23/367 ; H01L23/00 ; H01L23/522 ; H01L23/552 ; H01L25/10 ; H01L23/36 ; H01L23/538 ; H01L23/13 ; H01L23/373 ; H01L23/498

Abstract:
A PoP semiconductor device has a top semiconductor package disposed over a bottom semiconductor package. The top semiconductor package has a substrate and a first semiconductor die disposed over the substrate. First and second encapsulants are deposited over the first semiconductor die and substrate. A first build-up interconnect structure is formed over the substrate after depositing the second encapsulant. The top package is disposed over the bottom package. The bottom package has a second semiconductor die and modular interconnect units disposed around the second semiconductor die. A second build-up interconnect structure is formed over the second semiconductor die and modular interconnect unit. The modular interconnect units include a plurality of conductive vias and a plurality of contact pads electrically connected to the conductive vias. The I/O pattern of the build-up interconnect structure on the top semiconductor package is designed to coincide with the I/O pattern of the modular interconnect units.
Public/Granted literature
- US20160276307A1 Semiconductor Device and Method of Forming POP Semiconductor Device with RDL Over Top Package Public/Granted day:2016-09-22
Information query
IPC分类: