- Patent Title: Semiconductor device manufacturing method and semiconductor wafer
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Application No.: US15331957Application Date: 2016-10-24
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Publication No.: US09786630B2Publication Date: 2017-10-10
- Inventor: Yuichi Ota , Kentaro Kita , Takehiro Oura , Kohei Yoshida
- Applicant: Renesas Electronics Corporation
- Applicant Address: JP Tokyo
- Assignee: RENESAS ELECTRONICS CORPORATION
- Current Assignee: RENESAS ELECTRONICS CORPORATION
- Current Assignee Address: JP Tokyo
- Agency: Shapiro, Gabor and Rosenberger, PLLC
- Priority: JP2015-250866 20151224
- Main IPC: H01L21/768
- IPC: H01L21/768 ; H01L23/544 ; H01L23/00 ; H01L21/683 ; H01L21/8238 ; H01L21/304 ; H01L21/78
Abstract:
A semiconductor device manufacturing method improves the yield of manufacturing semiconductor devices. There are provided an insulating film for covering multiple bonding pads, a first protective film over the insulating film, and a second protective film over the first protective film. In semiconductor chips, multiple electrode layers are coupled electrically to each of the bonding pads via first openings formed in the insulating film and second openings formed in the first protective film. Multiple bump electrodes are coupled electrically to each of the electrode layers via third openings formed in the second protective film. In pseudo chips, the second openings are formed in the first protective film and the third openings are formed in the second protective film. The insulating film is exposed at the bottom of the second openings coinciding with the third openings. A protective tape is applied to a principal plane to cover the bump electrodes.
Public/Granted literature
- US20170186725A1 SEMICONDUCTOR DEVICE MANUFACTURING METHOD AND SEMICONDUCTOR WAFER Public/Granted day:2017-06-29
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